1. Field of the Invention:
The present invention relates to a semiconductor memory circuit and, more particularly to a dynamic type random access memory circuit (DRAM) fabricated on a semiconductor substrate.
2. Description of the Related Art:
Dynamic memory circuits have been utilized in various fields as large capacity semiconductor memories. The dynamic memory circuit is typically constructed in such a manner that one-transistor type memory cells each composed of one transfer gate transistor and a capacitor are arranged in a matrix form of rows and columns with word lines arranged in rows and pairs of bit lines arranged in columns. In each memory cell, storage of information is conducted by existence or non-existence of electric charge in the capacitor. Reading of information is achieved by selecting one of the word lines so that electric charge of the memory cell connected to the selected word line is transferred to one bit line in the pair of bit lines of the same column as the selected memory cell with the other bit line set at a reference voltage. As a result, a small difference in voltage, normally 100 to 200 mV, is generated between the pair of bit lines. This small voltage difference is amplified by a sense amplifier. The amplified signal is read out via an output circuit and also is restored into the preselected memory cell for maintaining information storage.
The reference voltage is usually set at an intermediate level of logic "1" and "0" levels stored in the memory cells. Since the logic "1" and "0" levels are practically set at a power source voltage Vcc and a ground potential, respectively, the reference voltage is practically set at 1/2 Vcc level.
Several methods are available for providing the reference voltage. One of them is to produce the reference voltage by changing the potential of a dummy word line which is capacitively coupled to the bit lines. This method employs a memory configuration consisting of only one capacitive cell for each bit line, which is simple and suited for high-density integration. According to this method, the pair of bit lines which are amplified to the logic "1" (High) and "0" (Low) levels, respectively, during a time when an active period are short-circuited during a reset period subsequent to the active period. As a result, the pair of bit lines are precharged approximately to a 1/2 Vcc level. Then, in a subsequent active period, one of the dummy word lines is selectively fallen in potential to cause slight fall in potential at one bit line of the bit line pair with the other bit line to which a read signal from the selected memory cell is applied. More particularly, in the 1/2 Vcc precharging method, since the precharge potential at the bit lines is the intermediate potential between the bit line potential when stored information in the memory cell is high and the bit line potential when it is low, the precharge potential can theoretically be deemed as a reference potential and can be fed as it is to the sense amplifier. In reality, however, for many reasons, it is often desired that the reference potential be slightly lower than the bit line precharge potential (1/2 Vcc). Therefore, the dummy word line is made to have a capacitive element to provide a desired reference potential on the bit line. After this, the sense amplifier is activated and the differential voltage between the pair of bit lines with a result of, for example, one bit line at the power supply potential and the other bit line at the ground potential. At this time, the charge in the memory cell capacitor is recovered to the state before the readout operation, that is the memory cell capacitor becomes refreshed.
However, according to the above conventional method employing the dummy word line, there is a problem that, since a capacitive coupling is provided between the dummy word lines and the bit lines, which is identical to providing a capacitive coupling between the bit lines through the dummy word lines, the capacitive coupling forms a path for supplying changes in other bit line pairs as noises when the sense amplifier operates.
Generally, the sense amplifier's amplification or decision speeds for the high level and low level states of the memory cells are not equal because of memory layout and manufacturing factors. Further, the input differential voltage to the sense amplifier when the memory cell is high is not always equal to that when the memory cell is low. Suppose, as in the previous explanation, when the word line is selected, only one selected memory cell connected to one bit line pair is low with the remaining selected memory cells connected to other bit line pairs at a high level. In this case, the decision speed of the sense amplifier for that one selected memory cell at the low level is slow, so that the potential differences of other bit line pairs are amplified by the sense amplifiers before the potential difference of the one bit line pair becomes sufficiently large.
Thus, one stored state of the minority number of the selected memory cells affects the other state of the minority number of the selected memory cell or cells through the dummy word line and their associated capacitive elements. As a result, the operation speed of the memory circuit is lowered and effective sensitivity of the sense amplifiers is also lowered.
These problems will grow in severity as the memory capacity increases, i.e., as the number of pairs of bit lines sharing the dummy word lines and the wiring resistance of the dummy word lines increase.